1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device.
2. Description of the Related Art
The upper and lower semiconductor chips are electrically connected to each other by a through silicon via (TSV) provided so as to penetrate through the semiconductor chips is used, in a semiconductor device in which the functional upgrading is realized by stacking a plurality of semiconductor chips.
In such a semiconductor chip, an insulating ring structure in which a TSV is surrounded by an insulator is used in some cases for the purpose of insulating and isolating the TSV and an element region from each other and reducing capacitance between adjacent TSVs.
JP2007-123857A discloses a method of manufacturing a semiconductor device including a through silicon via provided with an insulating ring. In this patent document, there is disclosed a process of forming an insulating ring firstly (via-first method), and forming TSVs lastly (via-last method) after processes of element formation through to wiring formation. More specifically, a ring-shaped trench is first dug in a depth direction from the element-forming surface side of a silicon substrate, and then this trench is filled with an insulating film to form an insulating ring. Then, the silicon substrate, after processes of element formation on a substrate surface, wiring layer formation, and the like, is ground from the rear surface side thereof to thin the substrate. At this time, a supporting substrate (WSS: Wafer Support System) is provided on a surface of the substrate through an adhesion layer and the rear surface of the substrate is ground until the bottom of the insulating ring becomes exposed out of the rear surface. Consequently, the substrate is formed into a structure in which the insulating ring penetrates through the silicon substrate from the front surface to the rear surface thereof. Then, a TSV is formed inside the insulating ring from the rear surface side of the silicon substrate, so as to penetrate through the substrate.
The insulating ring formed by a via-first method is formed in the substrate to such a depth as to allow the insulating ring to penetrate through the thinned substrate. This depth reaches 30 to 50 μm, which is significantly deep, as compared with an isolation region (for example, an STI) or the like provided likewise by forming a trench in the substrate. A study made by the present inventor has proved that unintended substrate etching occurs in a beveled portion of the outer circumference of the substrate when such a deep trench is formed by a via-first method, and that this serves as a source of dust generation. This condition will be described below with reference to FIGS. 1 and 2.
As illustrated in FIG. 1, side edge (outer circumference; curved portion in the substrate's edge) 2 of substrate 1 in the radial direction thereof is referred to as “beveled portion,” and exists so as to surround chip region 3. FIG. 2 is a cross-sectional view illustrating the vicinity of the side edge of substrate 1 illustrated in FIG. 1. When a trench for an insulating ring is formed in the substrate by using photoresist film 4, the photoresist film after development needs to cover the beveled portion. As illustrated in FIG. 2A, unlike a usual principal surface of a substrate, however, a surface of beveled portion 2 is curved so as to connect the front and rear surfaces of the substrate to each other. In such beveled portion 2, an anomaly may arise in a developed pattern of photoresist film 4 on the grounds that the coating properties of photoresist film 4 are uneven, an exposure anomaly occurs due to the irregular reflection of exposure light, or the like. If any places not covered with photoresist film 4 arise in part of the beveled portion at this time due to the above-described anomaly of patterning, unintended etching works upon beveled portion 2 in a trench formation process, as shown by part 5 enclosed by a dotted line in FIG. 2B. This can be a source of dust generation.
As described above, the trench for a TSV insulating ring is particularly deep, and therefore, a large amount of silicon is etched away. Accordingly, the abovementioned dust generation becomes particularly problematic in a process of forming the trench for the insulating ring by a via-first method.